`timescale 10ns/1ns
module testbench();
	
	parameter VC_NUM_PER_PORT 		=	2;
	parameter PYLD_WIDTH 			=	32;
	parameter BUFFER_NUM_PER_VC	=	16;
	parameter MAX_PCK_SIZE			=	256;	//maximum packet size in word
	parameter FLIT_TYPE_WIDTH		=	2;
	parameter PORT_NUM				=	5;
	parameter X_NODE_NUM				=	4;
	parameter Y_NODE_NUM				=	3;
	parameter SW_X_ADDR				=	2;
	parameter SW_Y_ADDR				=	1;
	parameter FIFO_FULL_SIG_WIDTH	=	2* VC_NUM_PER_PORT;
	parameter VC_ID_WIDTH			=	VC_NUM_PER_PORT;
	parameter FLIT_WIDTH				=	PYLD_WIDTH+ FLIT_TYPE_WIDTH+VC_ID_WIDTH;
	parameter M_ADDR_SIZE			=	19;
	parameter S_ADDR_SIZE			=	2;
	
	
	
	reg 												reset;
	reg												clk;
	wire	[FLIT_WIDTH-1					:0] 	flit_out;     
	wire 		   			   					flit_out_wr;   
	reg 	[FIFO_FULL_SIG_WIDTH-1		:0]	flit_out_vc_full;
	reg	[FLIT_WIDTH-1					:0] 	flit_in;     // Data in
	reg 	    			   						flit_in_wr;   // Write enable
	wire 	[VC_NUM_PER_PORT-1			:0]	credit_out;								
	reg												s_chipselect; 
	reg												s_write;
	reg												s_read;
	reg 	[S_ADDR_SIZE-1	:0]					s_address;
	reg 	[31				:0] 					s_writedata; 
	wire 	[31				:0] 					s_readdata;
	wire 												s_waitrequest;
	
	//avalon master interface signals
	wire												m_chipselect; 
	wire												m_write;
	wire												m_read;
	wire 	[M_ADDR_SIZE-1					:0]	m_address;
	wire 	[31								:0] 	m_writedata; 
	wire 	[31								:0] 	m_readdata;
	reg												m_waitrequest;

	
	initial begin
		clk=0;
		forever clk=#10 ~clk;
	end

	
	nic #(
		.VC_NUM_PER_PORT 		(VC_NUM_PER_PORT),
		.PYLD_WIDTH 			(PYLD_WIDTH),
		.BUFFER_NUM_PER_VC	(BUFFER_NUM_PER_VC),
		.MAX_PCK_SIZE			(MAX_PCK_SIZE),	
		.FLIT_TYPE_WIDTH		(FLIT_TYPE_WIDTH),
		.PORT_NUM				(PORT_NUM),
		.X_NODE_NUM				(X_NODE_NUM),
		.Y_NODE_NUM				(Y_NODE_NUM),
		.SW_X_ADDR				(SW_X_ADDR),
		.SW_Y_ADDR				(SW_Y_ADDR),
		.M_ADDR_SIZE			(M_ADDR_SIZE),
		.S_ADDR_SIZE			(S_ADDR_SIZE)
	
	)
	the_nic
	(
	
		.reset(reset), 
		.clk(clk), 
		.flit_out(flit_out), 
		.flit_out_wr(flit_out_wr), 
		.flit_out_vc_full(flit_out_vc_full), 
		.flit_in(flit_in), 
		.flit_in_wr(flit_in_wr), 
		.credit_out(credit_out), 
		.s_chipselect(s_chipselect), 
		.s_write(s_write), 
		.s_read(s_read), 
		.s_address(s_address), 
		.s_writedata(s_writedata), 
		.s_readdata(s_readdata), 
		.s_waitrequest(s_waitrequest), 
		.m_chipselect(m_chipselect), 
		.m_write(m_write), 
		.m_read(m_read), 
		.m_address(m_address), 
		.m_writedata(m_writedata), 
		.m_readdata(m_readdata), 
		.m_waitrequest(m_waitrequest)
); 
	
	
	niosii_ram #(
		.DATA_WIDTH(32),
		.ADDR_WIDTH	(13)
	)
	the_ram
	(
		.address			(m_address[12:0]),
		.byteenable		(),
		.chipselect		(m_chipselect),
		.clk				(clk),
		.clken			(1'b1),
		.reset			(reset),
		.write			(m_write),
		.writedata		(m_writedata),
      .readdata		(m_readdata)
	);
	
	
	
	
	
	
	initial begin
		reset	=1;
		flit_out_vc_full=4'b1011;
		flit_in=0;     // Data in
		flit_in_wr=0;   // Write enable
						
		s_chipselect=0; 
		s_write=0;
		s_read=0;
		s_address=0;
		s_writedata=0; 
	
	#100 
	reset =0;
	#50
	
	//check if error flag is set
	@(posedge clk	)#1
		s_chipselect=1; 
		s_write=1;
		s_read=0;
		s_address=0;
		s_writedata={13'd10,19'H50}; 
		
	@(posedge clk	)#1
		s_chipselect=0; 
		s_write=0;
		s_read=0;
		s_address=0;
		s_writedata=0; 
		
		
	#100
	@(posedge clk )#1
	flit_in={2'b10,2'b01,32'h550};     // Data in
	flit_in_wr=1;   // Write enable
	
	@(posedge clk )#1
	flit_in={2'b00,2'b01,32'h551};     // Data in
	flit_in_wr=1;   // Write enable
	
	@(posedge clk )#1
	flit_in={2'b00,2'b01,32'h552};     // Data in
	flit_in_wr=1;   // Write enable
	
	@(posedge clk )#1
	flit_in={2'b00,2'b01,32'h553};     // Data in
	flit_in_wr=1;   // Write enable
	
	@(posedge clk )#1
	flit_in={2'b00,2'b01,32'h554};     // Data in
	flit_in_wr=1;   // Write enable
	
			
	@(posedge clk )#1
	flit_in=0;     // Data in
	flit_in_wr=0;   // Write enable	
		
		
	#180	
	
	//transfer packet to mem
	@(posedge clk	)#1
		s_chipselect=1; 
		s_write=1;
		s_read=0;
		s_address=0;
		s_writedata={13'd10,19'H50}; 
		
	@(posedge clk	)#1
		s_chipselect=0; 
		s_write=0;
		s_read=0;
		s_address=0;
		s_writedata=0; 
		
	#180	
	
	@(posedge clk )#1
	flit_in={2'b01,2'b01,32'h555};     // Data in
	flit_in_wr=1;   // Write enable
		
	@(posedge clk )#1
	flit_in=0;     // Data in
	flit_in_wr=0;   // Write enable	
	
	end

endmodule





